A high-speed, low-power interleaved trace-back memory for Viterbi Decoder

Abstract

This paper presents a high-speed, low-power traceback memory structure for a Viterbi Decoder. The new memory is based on an array of registers connected with traceback signals that decode the output bits on the fly. The traceback memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 mu m CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps.