Countering PCIe Gen. 3 Data Transfer Rate Imperfection Using Serial Data Interconnect

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dc.contributor.authorRahnama, Behnam
dc.contributor.authorSari, Arif
dc.contributor.authorMakvandi, Reza
dc.date.accessioned2026-02-06T18:28:59Z
dc.date.issued2013
dc.departmentDoğu Akdeniz Üniversitesi
dc.descriptionInternational Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE) -- MAY 09-11, 2013 -- Mevlana Univ, Konya, TURKEY
dc.description.abstractIn high-speed data links, serial communications are replacing parallel communications rapidly. High-speed serial data links include backplane links such as PCI express and computer networking including Ethernet interfaces. This study tries to propose new solution for interconnection switches which use specially in HPC systems using a new jitter free data transfer technique for Serialization and Deserialization channels instead of PCIe conventional links.
dc.identifier.endpage582
dc.identifier.isbn978-1-4673-5613-8
dc.identifier.isbn978-1-4673-5612-1
dc.identifier.scopusqualityN/A
dc.identifier.startpage579
dc.identifier.urihttps://hdl.handle.net/11129/11221
dc.identifier.wosWOS:000325948700106
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Science
dc.language.isoen
dc.publisherIEEE
dc.relation.ispartof2013 International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (Taeece)
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WoS_20260204
dc.subjectPCIe
dc.subjectSerial Data Link
dc.subjectMixing Clock with Data
dc.subjectHPC
dc.subjectGigabit Ethernet
dc.titleCountering PCIe Gen. 3 Data Transfer Rate Imperfection Using Serial Data Interconnect
dc.typeConference Object

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