Performance optimization of the nano-scale carry-skip adder based on quantum dots and its application in the upcoming Internet of Things

Abstract

Internet of Things (IoT) is a network of linked computers, electronic and mechanical equipment, objects, living things, and people that can exchange data without human-to-human or human-to-computer interaction. Real objects with sensors, computing power, software, and other technologies are called IoT when they connect to and exchange data with other systems and devices over the Internet or other communication networks. On the other hand, Quantum-dot Cellular Automata (QCA) is a highly appealing alternative to transistor-based technologies for future circuit design, thanks to its excellent performance and low power consumption characteristics. Therefore, researchers are trying to implement IoT-related circuits in this technology and take advantage of it. In IoT nodes, the circuits were previously designed based on transistors and used extensively are adder circuits and their various forms, such as carry-look-ahead adder, ripple carry adder, and Carry-Skip Adder (CSA). The proposed CSA is part of the bypass adder family, and its major goal in IoT devices is to reduce latency and power consumption. Designing CSA is a fascinating area of research in the QCA and IoT domains. In this research, we will offer nano-scale CSA designs based on logic gate structures. This CSA aids in improving system performance in terms of average power dissipation, area, and delay. This design has performed admirably in terms of physical qualities, particularly power usage. As a result, an ultra-low-power CSA is proposed, which employs a reduced number of cells and a smaller area while achieving the desired highly polarized output. All the circuits provided in the simulator software have been tested, and their correctness has been confirmed. 36 quantum cells were employed, and the adder's area with propagating signal is around 0.04 µm2. The latency is about 2 clock phases. Additionally, the CSA for IoT devices is roughly 0.4 µm2, which results in a delay of 17 clock phases and the need for 374 quantum cells. The suggested CSA reduces cell consumption by 64 %, improves latency by 15 %, and increases area by 85 %. Compared to a carry-look-ahead adder, the CSA is the only way to reduce the latency of a ripple carry adder with low effort. © 2023 Elsevier GmbH