Compact three-stage low-voltage low-power BiCMOS operational amplifier with inverted nested Miller compensation
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IEEE
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info:eu-repo/semantics/closedAccess
Abstract
This paper presents a three-stage, compact, and power-efficient 3 V BiCMOS operational amplifier (opamp) with rail-to-rail input and output stages. The opamp is designed to be loaded by a 20-pF capacitive load and the unity-gain bandwidth is 5.2 MHz at 62° phase margin. The bipolar output stage is designed to swing an output load current of -12 to 12 mA. The opamp have an open-loop voltage gain of 122 dB and a bandwidth -to-supply power ratio of 6.42 MHz/mW for the 20 pF capacitive load.
Description
Proceedings of the 1998 9th Mediterranean Electrotechnical Conference, MELECON. Part 2 (of 2) --
Keywords
Bandwidth, Bipolar transistors, Capacitance, CMOS integrated circuits, Electric currents, Electric potential, Semiconductor junctions, Inverted nested miller compensation, Rail to rail input stage, Rail to rail output stage, Operational amplifiers
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Proceedings of the Mediterranean Electrotechnical Conference - MELECON
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2
