Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)

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dc.contributor.authorAybay, I
dc.contributor.authorÇerkez, C
dc.contributor.authorHalici, U
dc.contributor.authorBadaroglu, M
dc.date.accessioned2026-02-06T18:16:42Z
dc.date.issued1998
dc.departmentDoğu Akdeniz Üniversitesi
dc.description13th International Symposium on Computer and Information Sciences (ISCIS 98) -- OCT 26-28, 1998 -- BELEK ANTALYA, TURKEY
dc.description.abstractIn this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process.
dc.identifier.endpage161
dc.identifier.isbn90-5199-405-2
dc.identifier.issn1383-7575
dc.identifier.orcid0000-0002-8740-3261
dc.identifier.scopusqualityN/A
dc.identifier.startpage157
dc.identifier.urihttps://hdl.handle.net/11129/8623
dc.identifier.volume53
dc.identifier.wosWOS:000078740500021
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Science
dc.language.isoen
dc.publisherI O S Press
dc.relation.ispartofAdvances in Computer and Information Sciences '98
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WoS_20260204
dc.titleHardware implementations of neural networks and the Random Neural Network Chip (RNNC)
dc.typeConference Object

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