Continuous time delta sigma modulators with reduced clock jitter sensitivity

Abstract

In this paper, a technique and method is presented to suppress the effect of clock-jitter in continuous-time delta-sigma modulators with switched-current (current-steering) digital to analogue converters. A behavioural, transistor-level and noise analysis are presented followed by circuit-level simulations. The proposed approach which is a switched-current type of digital to analogue conversion is fully compatible Kith CMOS processes and multi-bit operations which are Widely used in high speed applications. Moreover, having a pulse-shaped output signal does not introduce extra demands on the modulator and hence does not increase the modulator's power consumption. A third-order continuous-time Delta Sigma modulator with the proposed digital-to-analogue converter in its feedback was used for circuit-level simulations. Results proved the robustness of the technique in suppressing the clock-jitter effects.