Designing an efficient fault tolerance D-latch based on quantum dot cellular automata nanotechnology

Abstract

Recently, Complementary Metal-Oxide-Semiconductor (CMOS) technology is limited by many barriers such as short channel effects and high power dissipation. Therefore, many alternatives are proposed to solve these shortages. One of the potential alternatives to CMOS is Quantum-dot Cellular Automaton (QCA) where binary information is encoded by using the electron location in a square cell. However, three types of fault (cell misalignment, cell missing, and cell dislocation) may cause the failure of the QCA-based designs. On the other hand, D-latch is one of the basic circuits in designing larger components such as counters and memories. Therefore, in this paper, a new fault-tolerance QCA-based D-latch is proposed and its performance is evaluated. The obtained results using QCADesigner have revealed that the proposed design produce correct output and thereby can tolerate 86% single-cell omission defects. Also, it has acceptable performance regarding the two and three cellular defects.