Countering PCIe Gen. 3 data transfer rate imperfection using serial data interconnect

Abstract

In high-speed data links, serial communications are replacing parallel communications rapidly. High-speed serial data links include backplane links such as PCI express and computer networking including Ethernet interfaces. This study tries to propose new solution for interconnection switches which use specially in HPC systems using a new jitter free data transfer technique for Serialization and Deserialization channels instead of PCIe conventional links. © 2013 IEEE.