Countering PCIe Gen. 3 data transfer rate imperfection using serial data interconnect

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dc.contributor.authorRahnama, Behnam
dc.contributor.authorSari, Arif
dc.contributor.authorMakvandi, Reza
dc.date.accessioned2026-02-06T17:58:33Z
dc.date.issued2013
dc.departmentDoğu Akdeniz Üniversitesi
dc.description2013 International Conference on Technological Advances in Electrical, Electronics and Computer Engineering, TAEECE 2013 --
dc.description.abstractIn high-speed data links, serial communications are replacing parallel communications rapidly. High-speed serial data links include backplane links such as PCI express and computer networking including Ethernet interfaces. This study tries to propose new solution for interconnection switches which use specially in HPC systems using a new jitter free data transfer technique for Serialization and Deserialization channels instead of PCIe conventional links. © 2013 IEEE.
dc.identifier.doi10.1109/TAEECE.2013.6557339
dc.identifier.endpage582
dc.identifier.isbn9781467356121
dc.identifier.scopus2-s2.0-84882238931
dc.identifier.scopusqualityN/A
dc.identifier.startpage579
dc.identifier.urihttps://doi.org/10.1109/TAEECE.2013.6557339
dc.identifier.urihttps://search.trdizin.gov.tr/tr/yayin/detay/
dc.identifier.urihttps://hdl.handle.net/11129/7642
dc.indekslendigikaynakScopus
dc.language.isoen
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_Scopus_20260204
dc.subjectGigabit Ethernet
dc.subjectHPC
dc.subjectMixing Clock with Data
dc.subjectPCIe
dc.subjectSerial Data Link
dc.titleCountering PCIe Gen. 3 data transfer rate imperfection using serial data interconnect
dc.typeConference Object

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