A new bulk-driven input stage design for sub 1-volt CMOS op-amps

Abstract

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V(T0)+3V(DSsat)) to the maximum allowed for the CMOS process, as well as preventing latch-up.