A new bulk-driven input stage design for sub 1-volt CMOS op-amps

Simple item page
dc.contributor.authorHaga, Yasutaka
dc.contributor.authorMorling, Richard C. S.
dc.contributor.authorKale, Izzet
dc.date.accessioned2026-02-06T18:28:50Z
dc.date.issued2006
dc.departmentDoğu Akdeniz Üniversitesi
dc.descriptionIEEE International Symposium on Circuits and Systems -- MAY 21-24, 2006 -- Kos, GREECE
dc.description.abstractThis paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V(T0)+3V(DSsat)) to the maximum allowed for the CMOS process, as well as preventing latch-up.
dc.description.sponsorshipIEEE
dc.identifier.endpage1550
dc.identifier.isbn978-0-7803-9389-9
dc.identifier.issn0271-4302
dc.identifier.scopus2-s2.0-34547314458
dc.identifier.scopusqualityN/A
dc.identifier.startpage1547
dc.identifier.urihttps://hdl.handle.net/11129/11152
dc.identifier.wosWOS:000245413501256
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIEEE
dc.relation.ispartof2006 Ieee International Symposium on Circuits and Systems, Vols 1-11, Proceedings
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WoS_20260204
dc.titleA new bulk-driven input stage design for sub 1-volt CMOS op-amps
dc.typeConference Object

Files

Collections

WoS Indexed Publications Collection
Scopus İndeksli Yayınlar Koleksiyonu