A viterbi decoder with low-power trace-back memory structure for wireless pervasive communications

Abstract

This paper presents a new trace-back memory structure for Viterbi Decoder that reduces power consumption by 63% compares to conventional RAM based design. Instead of the intensive read and write operations as required in RAM based designs, the new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The structure is used together with appropriate clock and power-aware control signals. Based on a 0.35 mu m CMOS implementation the trace-back back memory consumes energy of 182 pJ.